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TSMC has announced that its cutting-edge 3nm process has entered pilot production. Volume production is scheduled for Q4 2022, with customers including Apple, Intel, AMD and Qualcomm.

Despite TSMC’s significant progress in advanced packaging, it still faces major hurdles, according to Dr. Douglas Yu, TSMC’s Vice-President responsible for system integration. 

Participating in an event hosted by SEMI, Dr. Yu identified two challenges faced by TSMC, mainly caused by the inevitable transition from front-end to back-end technologies as prompted by the advent of advanced packaging. Even though TSMC is already pursuing advanced manufacturing nodes beyond 3nm, when it comes to advanced packaging, it is still stuck at 2μm. Consequently, cost control and efficiency become a hurdle when TSMC uses frontend equipment, such as those for copper interconnect process, to facilitate heterogeneous integration. 

On the other hand, precision would pose a challenge if TSMC opted to use its traditional back-end process equipment to achieve heterogeneous integration. As linewidth continuously shrinks to nanometer scale, additional thermal process steps will be required to stack chips together, resulting in a change of wafer structure that ultimately impacts the precision of electrical connections. 

According to the TSMC Vice-President, TSMC’s current heterogeneous roadmap focuses on system scaling, including improving the density of die-to-die interconnects, shrinking the bonding pitch by 70% with every generation. A continuous increase in package size will be another focus.


Source: Anue